The Passive Optical Network (PON) is a point-to-multipoint optical fiber access technology, and has advantages such as easy maintenance, broad bandwidth and low cost. The PON is an ideal physical platform for accessing multiple services such as voice, data and video. The PON includes an Optical Line Terminal (OLT), an Optical Network Unit (ONU) and an Optical Distribution Network (ODN). Because ODN includes a passive optical splitter/coupler, PON does not require elements having amplification and relay functions.
The Ethernet Passive Optical Network (EPON) is a PON technique, which utilizes Ethernet protocols with mature and economical techniques, and has advantages such as easy maintenance, low cost, broadband transmission and better performance-price ratio. In the Ethernet protocol, a structure of an 802.3 Ethernet data frame corresponding to the EPON is illustrated in FIG. 1. There is a 4-byte Cyclic Redundancy Check (CRC) at the end, i.e. before the Extension portion, of each 802.3 Ethernet data frame. A receiver can detect certain errors according to the CRC result.
For improving the anti-jamming capability BER performance of the system and increasing the power budget of the system, at present the 10G EPON system being constituted by the Institute of Electrical and Electronics Engineers (IEEE) 802.3av employed forward error control (FEC) coding technique. The basic operation of the FEC technique is to add parity check bits to the end of a transmitting Ethernet data portion according to a predefined rule between the parity check portion and the data portion. The receiver, on receiving the Ethernet frame from the transmitter, verifies the association between the Ethernet data portion and the parity check portion of an FEC codeword according to the predefined rule. If finding the association is incorrect, i.e. the FEC decoding fails, the receiver determines that error occurs during the transmission of the Ethernet frame and indicates the uncorrectable data block.
Besides the above FEC coding technique, another coding technique, line coding is employed at the physical layer of the EPON system. The basic operation of the line coding is that the original input data is converted into data in a format that is receivable by the receiver. Meanwhile, the line coding must ensure that there is sufficient transition that can be provided to a clock recovery circuit. The encoder also provides a method for aligning data with word, and the line coded sequence can maintain good direct current balance. At present, in the 10G EPON system being constituted by the IEEE 802.3av workgroup, line coding mechanisms with higher coding rate such as 64b/66b and 64b/65b are employed. These two line coding mechanisms utilize a scrambler, where the synchronization character and control character of the two line coding mechanisms bypass the scrambler, i.e. the synchronization character does not change. According to the 64B/66B coding mechanism, a two-bit synchronization character (synchronization header) is added on the basis of 64-bit information. The two-bit synchronization character has only two values, “01” and “10”. The synchronization character “01” indicates that all of the 64-bit information is data information, the synchronization character “10” indicates that the 64-bit information includes data information and control information. The synchronization character “00” or “11” indicates that error occurs during the transmission. The usage of the synchronization character ensures that there is at least one transition at intervals of 66 bits, so as to facilitate block synchronization. The 64-bit information is scrambled with an auto-synchronization scrambling mechanism, which can ensure that there is sufficient transition for the transmitted data to an utmost extent for facilitating clock recovery. Being different from the 64B/66B coding mechanism, the 64B/65B coding utilizes a 1-bit data/control character. The data/control character “0” indicates that all the 64 bits are data information. The data/control character “1” indicates the 64-bit information includes data information and control information.
For the detection of known error at the Medium Access Control (MAC) layer via CRC verification, a control character /E/ with a length of one byte, is used in the standard of the IEEE 802.3 10G system. The control character /E/ indicates an error.
A schematic diagram of a corresponding relation between an open systems interconnection reference model and an IEEE 802.3 10G bit local area network model is illustrated in FIG. 2. At present, the 10G EPON system constituted by the IEEE 802.3av workgroup utilizes this model, the transmission rate at the physical layer of which reaches 10 Gbps.
As illustrated in FIG. 2, if the data received from the GIGABIT MEDIA INDEPENDENT INTERFACE (XGMII) by the Reconciliation Sublayer (RS) includes a control character /E/, it indicates that error occurs to the received data where the /E/ locates. To ensure that the RS can detect the error by the CRC checking of the 802.3 Ethernet data frame after the data arrives at the MAC layer, the RS needs to preprocess the received data. One of processing methods is to replace part of the data so that the error can be checked by CRC.
The control character /E/ may be inserted at the transmitting end, or be replaced at the receiving end. In case of 64/66b line coding technique, the control character /E/ is received and processed generally in the 66/64b line decoding module of the receiving end. As illustrated in FIG. 3, in the existing IEEE 802.3 10G Ethernet standard, the 66/64b line decoding module is located at the Physical Coding Sublayer (PCS).
At the physical layer of the existing IEEE 802.3 10G Ethernet standard, the 802.3 Ethernet data frame is identified by indicator /S/ and /T/. /S/ indicates a start of data frame, and /T/ indicates a termination of data frame. The 66/64b line decoding module determines that error occurs to a received data block, if the 66/64b line decoding module at the PCS layer of the receiver, after receiving a control character /S/ indicating a start of data frame, receives the data block containing a synchronization header “10”, including any control character except a control character /T/ indicating a termination of data frame, or if the 66/64b line decoding module at the PCS layer of the receiver receives an invalid data block having a synchronization header “00” or “11”. In this case, the 66/64b line decoding module replaces all eight bytes in the data block with control characters /E/. The above /S/, /T/ and /E/ have a length of one byte respectively.
The receiver of the 10G EPON system constituted by the IEEE802.3av workgroup has employed the 66/64b line decoding module, the XGMII and RS as well as the FEC coding technique at its PCS layer. However, there is no solution of how to indicate the uncorrectable data block to the line decoding module in the EPON system after the failure of FEC decoding.